Alibaba's research arm promises server-class RISC-V processor due this year (www.theregister.com)
from schizoidman@lemmy.ml to technology@lemmy.ml on 21 Mar 2024 00:56
https://lemmy.ml/post/13438710

cross-posted from: lemmy.ml/post/13412490

Alibaba’s research arm promises server-class RISC-V processor due this year

#technology

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delirious_owl@discuss.online on 21 Mar 2024 05:18 next collapse

Is it going to have IME equivalent or will this thing actually be safe?

pastermil@sh.itjust.works on 21 Mar 2024 07:06 next collapse

Alibaba’s research arm

server-class RISC-V processor

Is this on purpose?

qaz@lemmy.world on 21 Mar 2024 13:57 collapse

ARM is a type of RISCV, it makes sense their ARM division expands to other RISCV architectures.

EDIT: ARM is a type of RISC, not RISCV

billgamesh@lemmy.ml on 21 Mar 2024 14:11 next collapse

I can see where this came from. ARM and RISC-V are both reduced instruction set computer (RISC) architechtures but are not the same. Arm is a proprietary ISA originally from Acorn. Risc-v is a new ISA developed completely open-source

EDIT: also, not to be killjoy, but for clarity “research arm” means apendage or division and is completely unrelated

billgamesh@lemmy.ml on 21 Mar 2024 14:13 next collapse

en.m.wikipedia.org/wiki/Reduced_instruction_set_computer

sugar_in_your_tea@sh.itjust.works on 21 Mar 2024 14:25 collapse

I disagree. The simplest and best reading is they have an ARM CPU for research, and the CPU produced the RISC-V design.

billgamesh@lemmy.ml on 21 Mar 2024 16:49 collapse

Maybe we’re reading something different, or this is tongue and cheek but "Alibaba’s research arm, the Damo Academy, " sounds like research arm is a synonym for “research division” or “research department”.

sugar_in_your_tea@sh.itjust.works on 21 Mar 2024 16:51 collapse

Nope, definitely a CPU. It’s the CPU that’s promising the server-class RISC-V processor.

billgamesh@lemmy.ml on 21 Mar 2024 17:01 collapse

Where in that article do you read that?

sugar_in_your_tea@sh.itjust.works on 21 Mar 2024 17:19 collapse

The part where it says “arm.”

You’re really not getting the sarcasm here are you…

billgamesh@lemmy.ml on 21 Mar 2024 17:30 collapse

No, I was hoping it’d be confirmed when I mentiomed it could be tongue in cheek. Doesn’t always come across in a thread where some are unironically making the same point.

sugar_in_your_tea@sh.itjust.works on 21 Mar 2024 17:36 collapse

I was trying to criticize the original poster by using increasingly ridiculous arguments, when it was obvious they never actually read the article and even misread the post. Something something satire.

I guess it didn’t come off obvious enough. ¯\_(ツ)_/¯

billgamesh@lemmy.ml on 21 Mar 2024 19:38 collapse

I’m just bad at reading sarcasm sometimes. Probably you were obvious and it went over my head

onlinepersona@programming.dev on 21 Mar 2024 14:12 next collapse

Don’t you mean ARM is a type of RISC? (RISC = Reduced Instruction Set Computer)

CC BY-NC-SA 4.0

qaz@lemmy.world on 21 Mar 2024 20:23 collapse

Yes, I somehow wrote RISC-V instead of RISC 😅. You’re right.

vintageballs@feddit.de on 21 Mar 2024 14:13 next collapse

No it’s not. Arm is a RISC architecture. RISC-V also is a RISC architecture.

Arm is explicitly not RISC-V.

null@slrpnk.net on 21 Mar 2024 14:14 next collapse

Arm in this context doesn’t mean ARM.

pastermil@sh.itjust.works on 21 Mar 2024 14:32 collapse

With all the liberty to do some research before commenting, I’m rather disappointed to see such factually wrong comment.

qaz@lemmy.world on 21 Mar 2024 20:28 collapse

I did, I just accidentally wrote RISCV instead of RISC. The acronym ARM actually stands for “Acorn RISC Machine”. TheLowSpecGamer has an interesting animated series about it’s development that is worth checking out.

PipedLinkBot@feddit.rocks on 21 Mar 2024 20:30 collapse

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Crackhappy@lemmy.world on 21 Mar 2024 10:26 next collapse

That’s an admirable goal, and I applaud the immense effort undertaken to make the OSS dream true.

Moonrise2473@feddit.it on 21 Mar 2024 12:12 next collapse

I don’t think they’re doing this for oss reasons

I don’t think they’re even required to publish the design, they could keep it proprietary

timbuck2themoon@sh.itjust.works on 21 Mar 2024 20:06 collapse

They’re not. They’re doing it because they fear being SOL if America/the West enforces more sanctions on things like ARM chips/designs or Intel, etc.

And yes, IIRC RISC-V is MIT licensed or something close. Basically companies can take it and implement whatever on top and not have to contribute back.

stsquad@lemmy.ml on 21 Mar 2024 12:30 collapse

The ISA may be open but I’m pretty sure the microarchitecture will be totally proprietary. Even with a kick ass microarchitecture they may still struggle if they can’t use the latest process nodes to actually manufacture the chips.

Having said that I suspect the main challenge RISCV is going to face is the software ecosystem. That stuff can take a decade to build and requires a degrees of cooperation between all the companies building chips.

Linkerbaan@lemmy.world on 21 Mar 2024 19:45 collapse

RiscV has been used for small specific tasks but running a whole OS on it still seems far fetched with so many libraries being unsupported. (yes it exists already but that is also very limited in functionality)

merthyr1831@lemmy.world on 21 Mar 2024 20:03 collapse

You can run desktop linux on RISC-V. youtu.be/1apoFXZ9ad8?si=DMF37jRfUqRHRDm9

PipedLinkBot@feddit.rocks on 21 Mar 2024 20:05 collapse

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